1. Field of the Invention
The present invention relates to a liquid crystal display apparatus, more particularly to a configuration for lowering the parasitic capacitance of a signal line in an active matrix type liquid crystal display apparatus.
2. Description of the Related Art
Recently, a thin film transistor (hereinafter, referred to as "TFT") has been developed to be applied to an image display device such as a flat type display. Especially, a driver monolithic panel using a polysilicon TFT has been actively developed. The technology conventionally developed is described, for example, in Japanese Patent Publication No. 4-3552. Hereinafter, referring to FIG. 8, the apparatus disclosed in this publication will be described.
FIG. 8 is a block diagram showing a conventional active matrix type liquid crystal display apparatus 101 (hereinafter, referred to as "display apparatus") using TFTs. FIG. 9 is a diagram showing an electric equivalent circuit corresponding to each one of the pixels of the display apparatus 101. The display apparatus 101 includes a scanning substrate 103 and a counter substrate 113 opposed to each other, as well as a liquid crystal layer injected between the substrates 103 and 113. The peripheral portions of both of the substrates are sealed by a seal member. On the scanning substrate 103, a plurality of source bus lines 104 parallel with one another, and a plurality of gate bus lines 105 parallel with one another are disposed. The source bus lines 104 and the gate bus lines 105 perpendicularly cross each other. In the vicinity of each of the intersections between the source bus lines 104 and the gate bus lines 105, one pixel is disposed. Namely, a plurality of pixels are disposed in a matrix on the scanning substrate 103.
Each pixel includes an equivalent capacitance 106 of the liquid crystal layer and parasitic capacitances 107, 108 and 109. The parasitic capacitance 107 is a capacitance formed at the intersection between the source bus line 104 and the gate bus line 105. The parasitic capacitance 108 is a capacitance formed by the source bus line 104 and a counter electrode (not shown) on the counter substrate 113. The parasitic capacitance 109 is a capacitance formed by the gate bus line 105 and the counter electrode. Into the equivalent capacitance 106, an electric charge is injected through a pixel electrode 102. The pixel electrode 102 is connected to the drain electrode of a TFT 110 provided for each pixel. The gate electrode of the TFT 110 is connected to the gate bus line 105, while the source electrode thereof is connected to the source bus line 104. Each TFT 110 is electrically switched between conductive and non-conductive states by a scanning signal from the gate bus line 105. The source bus line 104 and the gate bus line 105 are connected to a data output circuit 111 and a scanning circuit 112, respectively.
The display apparatus 101 operates in the following manner. To the data output circuit 111, a video signal is input. This video signal has the polarity reversed for each horizontal scanning period. The data output circuit 111 samples the video signal at predetermined intervals during the horizontal scanning period. Also, the data output circuit 111 outputs the sampled video signal, in each of the horizontal scanning periods. The video signal applied to the source bus line 104 is held in the above-mentioned parasitic capacitances 107 and 108, so as to be written onto the capacitance 106 during a period when the TFT 110 is conductive.
In the conventional liquid crystal display apparatus operating in the above-mentioned manner, the sum of the parasitic capacitances 107 and 108 for each source bus line 104 is expressed by the following equation (1): EQU C=ng.times.(C.sub.gs +C.sub.s-bar) (1)
where, ng stands for the number of the gate bus lines 105, C.sub.gs stands for the capacitance of the parasitic capacitance 107, and C.sub.s-bar stands for the capacitance of the parasitic capacitance 108.
When the display apparatus is large-sized, the total parasitic capacitance of one source bus line 104, especially the capacitance C.sub.s-bar of the parasitic capacitance 108 increases, which results in a great load on the data output circuit 111. For this reason, it has been impossible to apply the conventional technology to a large-sized apparatus such as 10.4 type and 8.4 type. Also, in the case of a small-sized apparatus, when it is attempted to fabricate the apparatus for displaying a high definition image, the number of the gate bus lines 105 becomes large. This results in an increase in the number of the parasitic capacitances 107 located at the intersections between the gate bus lines 105 and the source bus lines 104. As a result, similar to a case of the large-sized apparatus, the driving ability of the data output circuit 111 is deteriorated.
As another conventional technology for overcoming such a problem, there is proposed a method in which a capacitor for holding the video signal is provided for each of the source bus lines 104 connected to the data output circuit 111, and an amplifier circuit is provided between each capacitor and the corresponding source bus line 104. However, the method leads to a rise in the consumption of electric power and an increase in the number of elements constituting the circuit. As a result, the deficiency ratio and the fabrication costs also increase.